1. Field
Example embodiments relate to a semiconductor memory device, and for example, to a semiconductor device and a random access memory (RAM) including fin-type channel regions. For example, the semiconductor device may include a fin field effect transistor (FinFET), and the RAM may include a dynamic random access memory (DRAM), a resistance random access memory (RRAM), a ferroelectric random access memory (FeRAM), or an NOR-type flash memory.
2. Description of Related Art
Fin field effect transistor (FinFET) structures which may enhance the performance of semiconductor devices have been studied.
FinFETs may use upper and/or side surfaces of a fin as a channel region. FinFETs may have a larger channel region than flat transistors, thereby allowing a greater current flow. Accordingly, FinFETs may perform better than flat transistors.
However, because conventional FinFETs may be manufactured using a silicon on insulator (SOI) substrate, a fin may float on a body of the SOI substrate. Accordingly, a threshold voltage of a transistor may not be controlled using a body bias, which may make it difficult to control a threshold voltage of a CMOS transistor. If the FinFETs are manufactured using a conventional bulk substrate, a drain depletion region may be expanded, thereby increasing junction leakage current, off-current, and/or junction capacitance. For example, a threshold voltage may be reduced and off current may be increased due to a short-channel effect in highly integrated semiconductor devices.
FinFETs may have higher contact resistance. For example, a conventional FinFET may include a plurality of bitline contacts crossing a plurality of fins. For example, the narrow upper surfaces of the bitline contacts and fins may contact one another. Accordingly, bitline contact resistance may be higher, and the fins may be bent to form the bitline contacts, thereby increasing manufacturing difficulty.
In a conventional FinFET, source and drain regions may be connected to fins and may be formed to secure a contact area. However, the distance between the fins may become greater due to the source and drain regions, which may reduce the integration density of the FinFET.